As the operating frequencies of modern computers continue to increase, power consumption by such computers increases accordingly. The relationship between power consumption and frequency is given in Equation 1.
P=CV2f xe2x80x83xe2x80x83(1)
In Equation 1, P represents power, C represents capacitance, V represents voltage, and f represents frequency. It is evident from Equation 1 that as f increases, P increases proportionally.
However, sometimes, increased power consumption may not be desirable or feasible at all parts of a computer system due to one or more system constraints, testing purposes, or performance concerns. For example, when power consumption is increased, temperature accordingly increases, and this may lead to diminished reliability. Further, due to increased power consumption at certain parts of the computer system, the supply of power at other parts of the computer system may be adversely affected. Thus, in order to avoid such problems caused by increased power consumption, frequency at particular parts of the computer system is decreased, i.e., xe2x80x9cdivided down.xe2x80x9d FIGS. 1a and 1b show a typical prior art approach to dividing down a frequency of a signal.
Specifically, FIG. 1a shows a frequency divider (10) that is formed by a positive edge-triggered D-Q flip-flop (also referred to as xe2x80x9cD-Q flip-flopxe2x80x9d) (12) and a delay stage (14), which is formed by an inverter (16). An input signal, CLK_IN, serves as an input to a clock input of the D-Q flip-flop (12). A Q output of the D-Q flip-flop (12), via FLIP_FLOP_OUT, serves as an input to the delay stage (14), which, in turn, outputs to both a D input of the D-Q flip-flop (12) and an output, CLK_OUT, of the frequency divider (10).
FIG. 1b shows a timing diagram (20) of the frequency divider (10) shown in FIG. 1a. If the D input to the D-Q flip-flop (12) is initially logic high, i.e., xe2x80x981xe2x80x99, when a first positive edge, i.e., a first xe2x80x9crisingxe2x80x9d edge, on CLK_IN (22) triggers the D-Q flip-flop (12), the D-Q flip-flop outputs logic high on FLIP_FLOP_OUT (24). The logic high on FLIP_FLOP_OUT (24) is inputted by the delay stage (14), which, in turn, inverts the logic high on FLIP_FLOP_OUT (24) and outputs logic low, i.e., xe2x80x980xe2x80x99, on CLK_OUT (26). The logic low outputted by the delay stage (14) also propagates to the D input of the D-Q flip-flop (12) to ready the D-Q flip-flop (12) for the next time it is triggered.
A next rising edge on CLK_IN (28) triggers the D-Q flip-flop (12) causing the D-Q flip-flop (12) to output logic low on FLIP_FLOP_OUT (30) due to the logic low at the D input of the D-Q flip-flop (12). The logic low on FLIP_FLOP_OUT (30) is inputted by the delay stage (14), which, in turn, inverts the logic low on FLIP_FLOP_OUT (30) and outputs logic high on CLK_OUT (32). The logic high outputted by the delay stage (14) also propagates to the D input of the D-Q flip-flop (12) to ready the D-Q flip-flop (12) for the next time it is triggered.
The description of the timing diagram (20) of FIG. 1b shows that the frequency of CLK_OUT is one-half that of CLK_IN. In other words, the frequency of CLK_OUT is equal to the frequency of CLK_IN divided by two. Essentially, the frequency divider (10) of FIG. 1a and other prior art frequency dividers generate an output signal by counting the number of cycle of an input signal. For example, the frequency divider (10) of FIG. 1a generates one cycle on an output signal for every two cycles on an input signal. Furthermore, the capability of most frequency dividers can be extended to allow the generation of multiple output signal frequencies, where the multiple output signal frequencies are generated by dividing down an input signal""s frequency by particular integer values.
FIG. 2a shows a typical prior art frequency divider (40) that is capable of generating multiple output signal frequencies. Specifically, FIG. 2a shows a frequency divider (40) that is formed by four negative edge-triggered J-K flip-flops (also individually referred to as xe2x80x9cJ-K flip-flopxe2x80x9d) (42, 44, 46, 48). The J and K inputs to the four J-K flip-flops (42, 44, 46, 48) are tied to logic high, and thus, every time a negative edge, i.e., a xe2x80x9cfallingxe2x80x9d edge, arrives at a clock input of one of the four J-K flip-flops (42, 44, 46, 48), the value stored inside that J-K flip-flop is inverted. The Q outputs of the first, second, and third J-K flip-flops (42, 44, 46) are connected to the clock inputs of the second, third, and fourth J-K flip-flops (44, 46, 48), respectively. Further, the signals from the Q outputs of the first, second, and third J-K flip-flops (42, 44, 46) are represented by C0, C1, and C2, respectively. The clock input of the first J-K flip-flop (42) is connected to an input signal, CLK, and the signal from the Q output of the fourth J-K flip-flop (48) is represented by C3.
FIG. 2b shows a timing diagram (50) of the frequency divider (40) shown in FIG. 2a. Initially, the four J-K flip-flops (42, 44, 46, 48) store a logic low. At a first falling edge of CLK (52), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic low to logic high, which results in logic high to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip-flop (44). Moreover, this logic high at the Q output of the first J-K flip-flop (42) causes C0 to go high (54). Thus, the first falling edge (52) at the clock input of the first J-K flip-flop (42) causes C0 to go high (54). However, the logic high on C0 (54) does not affect the value stored in the second J-K flip-flop (44) because the second J-K flip-flop (44) can only be triggered by a falling edge at its clock input.
At a second falling edge of CLK (56), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip-flop (44). Moreover, this logic low at the Q output of the first J-K flip-flop (42) causes C0 to go low (58) and triggers the second J-K flip-flop (44). Thus, because C0 goes high (54) at a first falling edge of CLK (52) and C0 goes low (58) at a second falling edge of CLK (56), CO""s frequency is one-half of CLK""s frequency. In other words, the frequency divider (40) can generate a signal that has a frequency equal to that of a clock signal""s frequency divided by two.
Because the second J-K flip-flop (44) is triggered by the falling edge on C0 (58), the value stored in the second J-K flip-flop (44) goes from logic low to logic high, which results in logic high to go from the Q output of the second J-K flip-flop (44) to the clock input of the third J-K flip-flop (46). Moreover, this logic high at the Q output of the second J-K flip-flop (44) causes C1 to go high (60). Thus, the second falling edge (56) at the clock input of the first J-K flip-flop (42) causes C0 to go low (58), which, in turn, triggers the second J-K flip-flop (44) and causes C1 to go high (60). However, the rising edge on C1 (60) does not affect the value stored in the third J-K flip-flop (46) because the third J-K flip-flop (46) can only be triggered by a falling edge at its clock input.
At a fourth falling edge of CLK (62), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip-flop (44). Moreover, this logic low at the Q output of the first J-K flip-flop (42) causes C0 to go low (64) and triggers the second J-K flip-flop (44).
Because the second J-K flip-flop (44) is triggered by the falling edge on C0 (64), the value stored in the second J-K flip-flop (44) goes from logic high to logic low, which results in logic low to go from the Q output of the second J-K flip-flop (44) to the clock input of the third J-K flip-flop (46). Moreover, this logic low at the Q output of the second J-K flip-flop (44) causes C1 to go low (66). Thus, the fourth falling edge (62) at the clock input of the first J-K flip-flop (42) causes C0 to go low (64), which, in turn, triggers the second J-K flip-flop (44) and causes C1 to go low (66). Furthermore, because C1 goes high (60) at a second falling edge of CLK (56) and C1 goes low (66) at a fourth falling edge of CLK (62), C1""s frequency is one-fourth of CLK""s frequency. In other words, the frequency divider (40) can generate a signal that has a frequency equal to that of a clock signal""s frequency divided by four.
Because C1 goes low (66), the third J-K flip-flop (46) is triggered and the value stored in the third J-K flip-flop (46) goes from logic low to logic high, which results in logic high to go from the Q output of the third J-K flip-flop (46) to the clock input of the fourth J-K flip-flop (48). Moreover, this logic high at the Q output of the third J-K flip-flop (46) causes C2 to go high (68). Thus, the fourth falling edge (62) at the clock input of the first J-K flip-flop (42) causes C0 to go low (64), which, in turn, causes C1 to go low (66), which, in turn, causes C2 to go high (68). However, the rising edge on C2 (68) does not affect the value stored in the third J-K flip-flop (46) because the third J-K flip-flop (46) can only be triggered by a falling edge at its clock input.
Those skilled in the art will understand that because the first J-K flip-flop (42) is pulsed at every falling edge of CLK and the second J-K flip-flop (44) is pulsed at every second falling edge of CLK, it follows that the third J-K flip-flop (46) is pulsed at every fourth falling edge of CLK and the fourth J-K flip-flop (48) is pulsed at every eighth falling edge of CLK. For instance, an eighth falling edge of CLK (70) causes C0 to go low (72), which, in turn, causes C1 to go low (74), which, in turn, causes C2 to go low (76), which, in turn, causes C3 to go high (78). Therefore, as shown in FIG. 2b, if CLK""s frequency is represented by f, then the frequency of C0 is f/2, the frequency of C1 is f/4, the frequency of C2 is f/8, and the frequency of C3 is f/16.
Based on Equation 1 given above, frequency and power consumption are directly related, and thus, the dividing down of f by a particular integer value automatically results in the dividing down of P by that particular integer value. Similar to the frequency divider (10) shown in FIG. 1a, the frequency divider (40) shown in FIG. 2a essentially generates divided down signals by counting the number of cycles of an original signal.
However, although various situations require that power consumption be decreased, dividing down an original frequency by an integer value may result in performance degradation in cases where peak performance occurs at a frequency value that is not equal to the original frequency divided by any integer value.
In one aspect, a frequency divider that is capable of dividing down a frequency of a signal by a non-integer value comprises a phase counter stage that counts phases of the signal, where the phase counter stage generates a signal edge when a certain number of phases have been counted, and where an output signal of the frequency divider is generated dependent on the signal edge generated by the phase counter stage.
In another aspect, a method for dividing down a frequency of a signal by a non-integer value comprises counting phases of the signal, where a phase counter stage generates a signal edge when a certain number of phases have been counted, and generating an output signal dependent on the signal edge generated by the phase counter stage.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.